Publications & Patents
Academic contributions and intellectual property
Throughout my academic and professional career, I have contributed to the field of microelectronics through various publications in IEEE conferences and journals. My research has primarily focused on Phase Locked Loops (PLLs), low-noise design techniques, and clock recovery systems for secure applications.
A Phase Locked Loop with Loop Bandwidth Enhancement for Low-Noise and Fast-Settling Clock Recovery
IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
This paper presents a novel Phase Locked Loop (PLL) architecture with enhanced loop bandwidth for clock recovery applications. The proposed design achieves both low-noise performance and fast settling time, which are typically conflicting requirements in PLL design. Experimental results demonstrate significant improvements in jitter performance while maintaining rapid lock acquisition.
A New Adaptation Scheme For Low Noise and Fast Settling Phase Locked Loop
IEEE Midwest Symposium on Circuit and Systems
This paper introduces an adaptive bandwidth control scheme for Phase Locked Loops that dynamically adjusts loop parameters based on operating conditions. The proposed approach enables optimal noise performance during steady-state operation while providing fast acquisition during frequency transitions. Implementation details and measurement results validate the effectiveness of the adaptation scheme.
A Low Noise Fast-Settling Phase Locked Loop with Loop Bandwidth Enhancement
IEEE-NEWCAS and TAISA Conference
This work presents a comprehensive analysis of bandwidth enhancement techniques for Phase Locked Loops. The paper explores the theoretical foundations and practical implementations of adaptive loop filter designs that can simultaneously achieve low noise performance and rapid settling. Simulation and measurement results demonstrate the effectiveness of the proposed approach in real-world applications.
A Differential 3.3V BICMOS Buffer with Current Consumption and Linearity Control for RF Mixer
IEEE International Conference on Microelectronics (ICM)
This paper presents a novel differential buffer design implemented in BICMOS technology for RF mixer applications. The proposed circuit features adjustable current consumption and linearity control, enabling optimization for different performance requirements. Measurement results demonstrate excellent linearity and noise performance across a wide range of operating conditions.
A 50MHz Phase Locked Loop with Adaptive Bandwidth for Jitter Reduction
IEEE International Conference on Microelectronics (ICM)
This paper describes the design and implementation of a 50MHz Phase Locked Loop with adaptive bandwidth control specifically optimized for jitter reduction in clock generation applications. The proposed architecture dynamically adjusts loop parameters to minimize output jitter while maintaining lock under varying operating conditions. Experimental results show significant improvements in jitter performance compared to conventional PLL designs.
Patents
Several patents related to secure analog design techniques and RF communication systems have been filed through my work at various companies. Due to confidentiality agreements, detailed information cannot be disclosed publicly.
The patents cover innovations in:
- Clock recovery circuits
- Side-channel attack countermeasures for secure elements
- Low-power RF transceiver architectures for contactless applications
- Secure random number generation techniques
- Tamper-resistant circuit designs